1. Field of the Invention
The present invention relates to programmable logic circuits, and in particular, relates to the design of efficient routing resources in a programmable logic circuit.
2. Discussion of the Related Art
Two examples of high density programmable logic devices ("PLDs") are the programmable Large Scale Integration (pLSI) devices and the in-system programmable Large Scale Integration (ispLSI) devices from Lattice Semiconductor Corporation, Hillsboro, Oreg. An ispLSI device is reprogrammable in its application without being removed from the circuit board. Programmable logic devices can also be implemented in both volatile and non-volatile memory technologies (e.g. electrical eraseable programmable read-only memory or E.sup.2 PROM). The high density programmable logic devicess, such as the pLSI and the ispLSI devices, are often referred to as "complex PLDs", as distinguished from a class of devices loosely referred to as "field programmable gate arrays" (FPGAs). In a complex PLD, programmable logic functions are configured by programming a number of programmable logic blocks, each programmble logic block is typically implemented by a gate array and has a number of input and output signals. In contrast, in an FPGA, the programmable logic functions are performed by a relatively large number of programmable logic units, each programmable logic unit receiving a relatively small number of logic signals and being implemented by a "look-up table" of logic functions, which is implemented by a relatively small number of logic gates or multiplexors.
One advantage of implementing a logic circuit in a complex PLD, rather than in an FPGA, is the predictable interconnect delay. In a complex PLD, interconnection between any two programmable logic blocks is provided by a global routing resource having predictable delay characteristics. Thus, the delay between any two portions of a circuit implemented in a complex PLD is predictable and substantially independent of which programmable logic block or blocks the two portions of the circuit are assigned.
In an FPGA, however, because of the large number of programmable logic blocks provided, more than one type of interconnection paths are typically provided. Each type of interconnection path in an FPGA has a different delay characteristic. For example, in one FPGA, interconnect resources of at least three levels of performance are provided: a) "direct lines" which is a connection between two neighboring programmable logic blocks, b) "local lines", which are interconnection paths servicing a small number of programmable logic blocks within a small locality in the FPGA, and c) "long lines" which reaches a greater distance than the local lines. The long lines are relatively scarce resource. Thus, because each programmable logic block in an FPGA implements only a relatively small logic function, a large number of programmable logic blocks are typically involved in implementing a circuit. Consequently, many interconnections between programmable logic blocks are required to provide the connectivity of the circuit. Futhrer, the connection path between any two portions of the circuit is often established by a combination of direct, local and long line connections. Since the partitioning of a circuit is seldom known prior to implementation, the interconnect delay for a circuit implemented in an FPGA is difficult to predict.
FIG. 1 shows a block diagram of a prior art complex PLD device 100, which can be implemented as either a pLSI device or an ispLSI device. As shown in FIG. 1, device 100 comprises 24 generic logic blocks (GLBs) A0-A7, B0-B7, C0-C7 and D0-D7. Each GLB includes a number of input terminals, a logic array for implementing logic functions and a number of output terminals. The signals at the GLB's input terminals originate either from the routing pool 101, or directly from input/output (I/O) pins, which are shown in FIG. 1 around the periphery of the device, e.g. I/O pin 102a. The signals of the output terminals of a GLB can be routed to both output routing pool 103 and routing pool 101. Output routing pool 103 routes signals between a group of GLBs and a group of I/O pins. Each I/O pin of pLSI device 100 is associated with an I/O cell, which is programmable to define whether the I/O pin is an input pin, an output pin or a bidirectional pin.
Routing pool 101 is a global interconnection resource for interconnecting the GLBs. Routing pool 101 receives input signals from both the I/O pins and the output terminals of the GLBs and provides the signals received to the input terminals of the GLBs. Routing pool 101 provides connectivity between any pair of GLBs in pLSI device 100. Because of its regular structure, routing pool 101 provides predictable and consistent delay between any pair of GLBs. However, because complete connectivity among GLBs is provided by routing pool 101, the size of routing pool 101 grows rapidly as the number of input signals to routing pool 101 increases. Hence, as the density of the pLSI device grows, the amount of silicon area dedicated for routing pool 101 increases undesirably. Further, as the size of routing pool 101 grows, the signal delay in transmission through routing pool 101 increases, while the AC switching current also increases. Neither the increase in signal delay, nor the increase in the AC switching current, is desirable.